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82008hkim 20071003-s00010 no.a0635-1/21 ver.1.01 lc877816a lc877812a LC877808A overview the lc877816a/12a/08a is an 8-bit single chip microcontroller with the following on-chip functional blocks: ? cpu: operable at a minimum bus cycle time of 250ns ? rom: 16 k/12k/8k bytes ? ram: 512 9 bits ? lcd controller/driver ? 16bit timer 2ch + 8bit timer 1ch or more ? synchronous serial i/o port (with automatic bl ock transmit/receive function) ? asynchronous/synchronous serial i/o port ? system clock divider ? 8-bit ad converter 9-channel ? 17-source 10-vectored interrupt system ? power save mode all of the above functions are fabricated on a single chip. features ? rom ? 16384 8 bits ? 12288 8 bits ? 8192 8 bits ? ram ? 512 9 bits ordering number : ena0635a cmos ic 16k/12k/8k-byte rom and 512-byte ram 8-bit 1-chip microcontroller specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.
lc877816a/12a/08a no.a0635-2/21 ? minimum bus cycle time ? 250ns (4mhz) note: the bus cycle time indicates rom read time. ? minimum instruction cycle time (tcyc) ? 750ns (4mhz) ? power save mode ? power save mode is available, when system clock is rc oscillation or crystal oscillation. ? ports ? input/output ports data direction programmable for each bit individually: 12 (p1n, p70 to p73) data direction programmable in nibble units: 8 (p0n) (when n-channel open drain output is selected, data can be input in bit units.) ? lcd ports segment output: 24 (s00 to s23) common output: 4 (com0 to com3) bias terminals for lcd driver 5 (v1 to v3, cup1, cup2) other functions input/output ports: 8(pcn) ? oscillator pins: 4 (cf1, cf2, xt1, xt2) ? reset pin: 1 ( res ) ? power supply: 4 (v ss 1 to 2, v dd 1 to 2) 1 (vdc) ? lcd controller ? seven display modes are available. ? segment output (s16 to s23) can be switched to general purpose input/output ports. ? duty: 1/3duty, 1/4duty ? bias: 1/2bias, 1/3bias ? lcd power 1) 1/3bias v1: 1.2v to 1.8v v2: 2.4v to 3.6v v3: 3.6v to 5.4v 2) 1/2bias v1: 1.2v to 1.8v v2: 2.4v to 3.6v v3: 2.4v to 3.6v (connect v2 and v3) ? timers ? timer 0: 16 bit timer/counter with capture register mode 0: 2 channel 8-bit timer with programmable 8 bit prescaler and 8 bit capture register mode 1: 8 bit timer with 8 bit programmab le prescaler and 8 bit capture register + 8 bit counter with 8-bit capture register mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register mode 3: 16 bit counter with 16 bit capture register ? timer 1: pwm/16 bit timer/counter with toggle output function mode 0: 2 channel 8 bit timer/counter (with toggle output) mode 1: 2 channel 8 bit pwm mode 2: 16 bit timer/counter (with toggle output) toggle output from lower 8 bits is also possible. mode 3: 16 bit timer (with toggle output) lower order 8 bits can be used as pwm. ? timer 4: 8-bit timer with 6-bit prescaler ? timer 5: 8-bit timer with 6-bit prescaler ? timer 6: 8-bit timer with 6-bit prescaler (with toggle output) ? timer 7: 8-bit timer with 6-bit prescaler (with toggle output) continued on next page.
lc877816a/12a/08a no.a0635-3/21 continued from preceding page. ? base timer 1) the clock signal can be selected from any of the following : sub-clock (32.768khz crystal oscillator), system clock, and prescaler output from timer 0 2) interrupts of five different time intervals are possible. ? sio ? sio0: 8 bit synchronous serial interface 1) lsb first/msb first is selectable 2) internal 8 bit baud rate generator (fastest clock period 4/3 tcyc) 3) consecutive automatic data communication (1 to 256 bits) ? sio1: 8 bit asynchr onous/synchronous serial interface mode 0: synchronous 8 bit serial i/o (2-wire or 3-wire, transmit clock 2 to 512 tcyc) mode 1: asynchronous serial i/o (half duplex, 8 data bits, 1 stop bit, baud rate 8 to 2048 tcyc) mode 2: bus mode 1 (start bit, 8 data bits, transmit clock 2 to 512 tcyc) mode 3: bus mode 2 (start detection, 8 data bits, stop detection) ? ad converter: ? 8 bits 9 channels ? remote control receiver circuit (co nnected to p73/in t3/t0in terminal) ? noise rejection function (noise rejection filter?s time constant can be selected from 1/32/128 tcyc) ? watchdog timer ? watchdog timer can produce interrupt or system reset. ? watchdog timer has two types. 1) use an external rc circuit 2) use the microcontroller?s base timer ? interrupts ? 17 sources, 10 vectors 1) three priority (low, high and highest) multiple interrupt s are supported. during inte rrupt handling, an equal or lower priority interrupt request is postponed. 2) if interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence. in the case of equal priority levels, the v ector with the lowest address takes precedence. no. vector address level interrupt source 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/t0l 4 0001bh h or l int3/base timer 5 00023h h or l t0h 6 0002bh h or l t1l/t1h 7 00033h h or l sio0 8 0003bh h or l sio1 9 00043h h or l adc/t6/t7 10 0004bh h or l port 0/t4/t5 ? priority levels x > h > l ? for equal priority levels, vector w ith lowest address takes precedence. ? subroutine stack levels ? 256 levels maximum (the stack is allocated in ram) ? high-speed multiplication/division instructions ? 16 bits 8 bits (5 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? 16 bits 8 bits (8 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time)
lc877816a/12a/08a no.a0635-4/21 ? oscillation circuits ? on-chip rc oscillation for system clock use. ? cf oscillation (4mhz) for system clock use. (rf built in) ? crystal oscillation (32.768khz) low speed system clock use. (rf built in) ? system clock divider function ? low power consumption operation is available ? minimum instruction cycle time (0.75 s, 1.5 s, 3 s, 6 s, 12 s, 24 s, 48 s, 96 s, 192 s can be switched by program (when using 4mhz main clock) ? standby function ? halt mode: halt mode is used to reduce power consumption. during the halt mode, program execution is stopped but peripheral circuits keep operating (some parts of serial transfer operation stop.) 1) oscillation circuits are not stopped automatically. 2) released by the system reset or interrupts. ? hold mode: hold mode is used to reduce power consumption. program execution and peripheral circuits are stopped. 1) cf, rc and crystal oscillation circuits stop automatically. 2) released by any of the following conditions. (1) low level input to the reset pin (2) specified level input to one of int0, int1, int2 (3) port 0 interrupt ? x'tal hold mode: x?tal hold mode is used to reduce power consumption. program execution is stopped. all peripheral circuits excep t the base timer are stopped. 1) cf and rc oscillation circuits stop automatically. 2) crystal oscillator operation is kept in its state at hold mode inception. 3) released by any of the following conditions (1) low level input to the reset pin (2) specified level input to one of int0, int1, int2 (3) port 0 interrupt (4) base-timer interrupt ? development tools ? on chip debugger (lc87f7032a) lc87f7032a and lc877816a differ in following points. when lc87f7032a is power save mode, current consumption doesn?t decrease. when lc87f7032a is power save mode, x?tal voltage level doesn?t change. lc87f7032a has p2 registers (p2, p2ddr). but, lc877816a doesn?t have them. ? package form ? qfp64j(7 7): lead-free type ? qip64e(14 14): lead-free type
lc877816a/12a/08a no.a0635-5/21 package dimensions unit : mm (typ) 3289 package dimensions unit : mm (typ) 3159a sanyo : tqfp64j(7x7) 7.0 9.0 7.0 9.0 0.125 0.5 0.16 0.4 (0.5) (1.0) 1.2max 0.1 1 16 33 48 17 64 32 49 sanyo : qip64e(14x14) 14.0 17.2 14.0 17.2 0.15 0.35 0.8 (2.7) 3.0max 0.1 0.8 (1.0) 116 17 32 33 48 49 64
lc877816a/12a/08a no.a0635-6/21 pin assignment sanyo: tqfp64j(7 7) ?lead-free type? sanyo: qip64e(14 14) ?lead-free type? s23/pc7 s22/pc6 s21/pc5 s20/pc4 s19/pc3 s18/pc2 s17/pc1 s16/pc0 s15 s14 s13 s12 s11 s10 s09 s08 s07 s06 s05 s04 s03 s02 s01 s00 com3 com2 com1 com0 v3 v2 v1 vdc res xt1 xt2 v ss 1 cf1 cf2 v dd 1 p00/an0 p01/an1 p02/an2 p03/an3 p04/an4 p05/cko/dbgp0 p06/t6o/dbgp1 p07/t7o/dbgp2 nc p70/int0/t0lcp/an5 p71/int1/t0hcp/an6 p72/int2/t0in/an7 p73/int3/t0in/an8 v dd 2 v ss 2 p10/so0 p11/si0/sb0 p12/sck0 p13/so1 p14/si1/sb1 p15/sck1 p16/t1pwml p17/t1pwmh cup1 cup2 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 4 8 47 4 6 4 5 44 4 3 42 41 4 0 39 38 3 7 36 35 3 4 33 1 2 3 4 5 67 8 9 10 11 12 13 14 15 16 lc877816a lc877812a LC877808A top view
lc877816a/12a/08a no.a0635-7/21 system block diagram interrupt control standby control ir pla clock generator cf rc x?tal bus interface port 0 port 1 sio0 sio1 timer 0 timer 1 lcd controller alu rom pc acc b register c register psw rar ram stack pointer watchdog timer base timer int0 to 3 noise rejection filter adc timer 4 timer 5 timer 6 timer 7 port 7
lc877816a/12a/08a no.a0635-8/21 pin description pin name i/o function option v ss 1, v ss 2 - - power supply no v dd 1, v dd 2 - + power supply no vdc - + power supply no cup1, cup2 - ? capacitor connecting terminals for step-up/step-down no port0 p00 to p07 i/o ? 8bit input/output port ? data direction programmable in nibble units ? use of pull-up resistor can be specified in nibble units ? input for hold release ? input for port 0 interrupt ? other pin functions input for adc channel (an0 to an4) p05: clock output (system clock/subclock) when it?s lc87f7032a, p05 uses as dbgp0. p06: timer 6 toggle output when it?s lc87f7032a, p06 uses as dbgp1. p07: timer 7 toggle output when it?s lc87f7032a, p07 uses as dbgp2. yes port1 p10 to p17 i/o ? 8bit input/output port ? data direction programmable for each bit ? use of pull-up resistor can be specified for each bit individually ? other pin functions p10: sio0 data output p11: sio0 data input or bus input/output p12: sio0 clock input/output p13: io1 data output p14: sio1 data input or bus input/output p15: sio1 clock input/output p16: timer 1 pwml output p17: timer 1 pwmh output/buzzer output yes ? 4bit input/output port ? data direction can be specified for each bit ? use of pull-up resistor can be specified for each bit individually ? other functions p70: int0 input/hold release input/timer 0l capture input/output for watchdog timer/an5 p71: int1 input/hold release i nput/timer 0h capture input/an6 p72: int2 input/hold release input/timer 0 event input/timer 0l capture input/an7 p73: int3 input (noise rejectio n filter attached)/timer 0 event input/timer 0h c apture input/an8 input for adc channel (an5 to an8) ? interrupt acknowledge type rising falling rising & falling h level l level int0 int1 int2 int3 enable enable enable enable enable enable enable enable disable disable enable enable enable enable disable disable enable enable disable disable port7 p70 to p73 i/o no s0 to s15 o ? segment output for lcd no s16/pc0 to s23/pc7 i/o ? segment output for lcd ? can be used as general purpose input/output port (pc) no com0 to com3 o ? common output for lcd no v1 to v3 i/o ? lcd output bias power supply ? capacitor connecting terminals for step-up/step-down no res i ? reset terminal no xt1 i ? input for 32.768khz crystal oscillation ? when not in use, connect to v dd 2 no xt2 i/o ? output for 32.768khz crystal oscillation ? when not in use, set to oscillation mode and leave open no cf1 i ? input terminal for ceramic oscillator ? when not in use, connect to v dd 2 no cf2 o ? output terminal for ceramic oscillator ? when not in use, leave open no
lc877816a/12a/08a no.a0635-9/21 port output types port form and pull-up resistor options are shown in the following table. port status can be read even when port is set to output mode. port name option selected in units of option type output type pull-up resistor 1 cmos programmable(note 1) p00 to p07 1 bit 2 nch-open drain no 1 cmos programmable p10 to p17 1 bit 2 nch-open drain programmable p70 - no nch-open drain programmable p71 to p73 - no cmos programmable 1 cmos 2 pch-open drain s16(pc0) to s23(pc7) - 3 nch-open drain no note 1: attachment of port0 programmable pull-up resistors is controllable in nibble units (p00 to 03, p04 to 07). *1: connect as follows to reduce noise on v dd . v ss 1 and v ss 2 must be connected together and grounded. *2: the power supply for the internal memory is vdc. v dd 1 and v dd 2 are used as the power supply for ports. when v dd 1 and v dd 2 are not backed up, the port level does not beco me ?h? even if the port latch is in the ?h? level. therefore, when v dd 1 and v dd 2 are not backed up and the port latch is ?h? level, the port level is unstable in the hold mode, and the back up time becomes shorter because th e through current runs from v dd to gnd in the input buffer. if v dd 1 and v dd 2 are not backed up, output ?l? by the program or pull the port to ?l? by the external circuit in the hold mode so that the port level becomes ?l? level and unnecessary current consumption is prevented. lsi v dd 1 v dd 2 v ss 2 v ss 1 power supply v1 v2 v3 vdc cup1 cup2 back up capacitors *2
lc877816a/12a/08a no.a0635-10/21 absolute maximum ratings at ta = 25c, v ss 1 = v ss 2 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit supply voltage v dd max v dd 1, v dd 2, v2 v dd 1=v dd 2=v2 -0.3 +4.3 v1 -0.3 1/2 v dd v2 -0.3 v dd supply voltage for lcd vlcd v3 -0.3 3/2 v dd input voltage v i xt1, cf1, res -0.3 v dd +0.3 input/output voltage v io (1) ? ports 0, 1, 7, c -0.3 v dd +0.3 v peak output current ioph(1) ports 0, 1, 7, c ? cmos output selected ? current at each pin -4 ioah(1) port 7 total of all pins -10 ioah(2) port 0 total of all pins -25 ioah(3) port 1 total of all pins -25 high level output current total output current ioah(4) port c total of all pins -15 iopl(1) ports 02 to 07 port 1, 7, c current at each pin 6 peak output current iopl(2) port 00, 01 current at each pin 15 ioal(1) port 7 total of all pins 10 ioal(2) port 0 total of all pins 35 ioal(3) port 1 total of all pins 25 low level output current total output current ioal(4) port c total of all pins 15 ma tqfp64j(7 7) 200 allowable power dissipation pd max qip64e(14 14) ta=-30 to +70c 420 mw operating ambient temperature topr -30 +70 storage ambient temperature tstg -55 +125 c note 1-1: the average current per applicable pin must not exceed 1ma
lc877816a/12a/08a no.a0635-11/21 allowable operating conditions at ta = -30c to +70c, v ss 1 = v ss 2 = 0v specification parameter symbol pin/remarks conditions v dd min typ max unit v dd (1) 0.37 s tcyc 200 s 3.0 3.6 v dd (2) v dd 1=v dd 2=v2 normal mode 0.75 s tcyc 200 s 2.4 3.6 v dd (3) 2.25 s tcyc 200 s 3.0 3.6 operating supply voltage range v dd (4) v dd1 =v dd 2=v2 power save mode 4.28 s tcyc 200 s 2.4 3.6 supply voltage range in hold mode vhd v dd 1=v dd 2=v2 keep ram and register data in hold mode. 2.2 3.6 v ih (1) ? ports 1 ? p71 to p73 ? port 70 input/interrupt output disable 2.4 to 3.6 0.3v dd +0.7 v dd v ih (2) ? ports 0, c output disable 2.4 to 3.6 0.3v dd +0.7 v dd v ih (3) port 70 watchdog timer output disable 2.4 to 3.6 0.9v dd v dd input high voltage v ih (4) xt1, cf1, res 2.4 to 3.6 0.75v dd v dd v il (1) ? ports 1 ? p71 to p73 ? port 70 input/interrupt output disable 2.4 to 3.6 v ss 0.2v dd v il (2) ? ports 0, c output disable 2.4 to 3.6 v ss 0.2v dd v il (3) port 70 watchdog timer output disable 2.4 to 3.6 v ss 0.8v dd -1.0 input low voltage v il (4) xt1, cf1, res 2.4 to 3.6 v ss 0.25v dd v 3.0 to 3.6 2.25 200 operation cycle time tcyc (note 2-1) power save mode 2.4 to 3.6 4.28 200 s external system clock frequency fexcf(1) cf1 ? cf2 open ? system clock divider:1/1 ? external clock duty=50 5% ? normal mode 2.4 to 3.6 0.1 4 mhz fmcf cf1, cf2 4mhz ceramic resonator oscillation see fig. 1 2.4 to 3.6 4 mhz fmrc rc oscillation v dd =3.0v, ta=25 c 2.4 to 3.6 300 500 700 khz oscillation frequency range (note 2-2) fsx?tal xt1, xt2 32.768khz crystal resonator oscillation see fig. 2 2.4 to 3.6 32.768 khz note 2-1: relationship between tcyc and oscillation frequency is 3/fmcf at a division ratio 1/1 and 6/fmcf at a division ratio of 1/2. note 2-2: see table 1 and 2 for the oscillation constants.
lc877816a/12a/08a no.a0635-12/21 electrical characteristics at ta = -30c to +70c, v ss 1 = v ss 2 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit i ih (1) ? ports 0, 1, 7 ? port c ? res ? output disabled ? pull-up resister off. ? v in =v dd (including off state leak current of the output tr.) 2.4 to 3.6 1 i ih (2) xt1, xt2 when configured as an input port v in =v dd 2.4 to 3.6 1 high level input current i ih (3) cf1 v in =v dd 2.4 to 3.6 8 i il (1) ? ports 0, 1, 7 ? port c ? res ? output disabled ? pull-up resister off. ? v in =v ss (including off state leak current of the output tr.) 2.4 to 3.6 -1 i il (2) xt1, xt2 when configured as an input port v in =v ss 2.4 to 3.6 -1 low level input current i il (3) cf1 v in =v ss 2.4 to 3.6 -8 a i oh =-0.4ma 3.0 to 3.6 v dd -0.4 v oh(1) ports 0, 1, 7 cmos output option i oh =-0.2ma 2.4 to 3.6 v dd -0.4 high level output voltage v oh (2) port c i oh =-0.1ma 2.4 to 3.6 v dd -0.4 i ol =1.6ma 3.0 to 3.6 0.4 v ol (1) ports 0, 1, 7 i ol =0.8ma 2.4 to 3.6 0.4 i ol =5.0ma 3.0 to 3.6 0.4 v ol (2) p00, p01 i ol =2.5ma 2.4 to 3.6 0.4 low level output voltage v ol (3) port c i ol =0.1ma 2.4 to 3.6 0.4 vodls s0 to s23 i o =0ma v1, v2, v3 lcd level output 2.4 to 3.6 0 0.2 lcd output voltage regulation vodlc com0 to com3 i o =0ma v1, v2, v3 lcd level output 2.4 to 3.6 0 0.2 v resistance of pull-up mos tr. rpu ? ports 0, 1, 7 v oh =0.9v dd 2.4 to 3.6 25 50 200 k hysterisis voltage vhys ? ports 1, 7 ? res 2.4 to 3.6 0.1 v dd v pin capacitance cp all pins ? all other terminals connected to v ss . ? f=4mhz ? ta=25 c 2.4 to 3.6 10 pf
lc877816a/12a/08a no.a0635-13/21 serial i/o characteristics at ta = -30c to +70c, v ss 1 = v ss 2 = 0v 1. sio0 serial i/o characteristics (note 4-1-1) specification parameter symbol pin/remarks conditions v dd min typ max unit frequency tsck(1) 2 low level pulse width tsckl(1) 1 tsckh(1) see fig. 6. 1 input clock high level pulse width tsckha(1) sck0(p12) ? continuous data transmission/reception mode ? see fig. 6. ? (note 4-1-2) 2.4 to 3.6 4 frequency tsck(2) 4/3 tcyc low level pulse width tsckl(2) 1/2 tsckh(2) ? cmos output selected ? see fig. 6. 1/2 tsck serial clock output clock high level pulse width tsckha(2) sck0(p12) ? continuous data transmission/reception mode ? cmos output selected ? see fig. 6. 2.4 to 3.6 tsckh(2) +2tcyc tsckh(2) +(10/3) tcyc tcyc data setup time tsdi(1) 2.4 to 3.6 0.03 serial input data hold time thdi(1) sb0(p11), si0(p11) ? must be specified with respect to rising edge of sioclk. ? see fig. 6. 2.4 to 3.6 0.03 tdd0(1) ? continuous data transmission/reception mode ? (note 4-1-3) 2.4 to 3.6 (1/3)tcyc +0.05 input clock tdd0(2) ? synchronous 8-bit mode ? (note 4-1-3) 2.4 to 3.6 1tcyc +0.05 serial output output clock output delay time tdd0(3) so0(p10), sb0(p11) ? (note 4-1-3) 2.4 to 3.6 (1/3)tcyc +0.15 s note 4-1-1: these specifications are theoretical values. add margin depending on its use. note 4-1-2: to use serial-clock-input in continuous trans/rec mode, a time from si0run being set when serial clock is "h" to the first negative edge of the serial clock must be longer than tsckha. note 4-1-3: must be specified with respect to falling edge of sioclk. must be specified as the time to the beginning of output state change in open drain output mode. see fig. 6.
lc877816a/12a/08a no.a0635-14/21 2. sio1 serial i/o characteristics (note 4-2-1) specification parameter symbol pin/remarks conditions v dd min typ max unit frequency tsck(3) 2 low level pulse width tsckl(3) 1 input clock high level pulse width tsckh(3) sck1(p15) see fig. 6. 2.4 to 3.6 1 frequency tsck(4) 2 tcyc low level pulse width tsckl(4) 1/2 serial clock output clock high level pulse width tsckh(4) sck1(p15) ? cmos output selected ? see fig. 6. 2.4 to 3.6 1/2 tsck data setup time tsdi(2) 2.4 to 3.6 0.03 serial input data hold time thdi(2) sb1(p14), si1(p14) ? must be specified with respect to rising edge of sioclk. ? see fig. 6. 2.4 to 3.6 0.03 serial output output delay time tdd0(4) so1(p13), sb1(p14) ? must be specified with respect to falling edge of sioclk. ? must be specified as the time to the beginning of output state change in open drain output mode. ? see fig. 6. 2.4 to 3.6 (1/3)tcyc +0.05 s note 4-2-1: these specifications are theoretical values. add margin depending on its use. pulse input conditions at ta = -30c to +70c, v ss 1 = v ss 2 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit tpih(1) tpil(1) int0(p70), int1(p71), int2(p72) ? condition that interrupt is accepted ? condition that event input to timer 0 is accepted 2.4 to 3.6 1 tpih(2) tpil(2) int3(p73) (noise rejection ratio is 1/1.) ? condition that interrupt is accepted ? condition that event input to timer 0 is accepted 2.4 to 3.6 2 tpih(3) tpil(3) int3(p73) (noise rejection ratio is 1/32.) ? condition that interrupt is accepted ? condition that event input to timer 0 is accepted 2.4 to 3.6 64 tpih(4) tpil(4) int3(p73) (noise rejection ratio is 1/128.) ? condition that interrupt is accepted ? condition that event input to timer 0 is accepted 2.4 to 3.6 256 tcyc high/low level pulse width tpil(5) res ? condition that reset is accepted 2.4 to 3.6 200 s
lc877816a/12a/08a no.a0635-15/21 ad converter characteristics at ta = -30c to +70c, v ss 1 = v ss 2 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit resolution n 2.4 to 3.6 8 bit absolute accuracy et (note 6-1) 2.4 to 3.6 1.5 lsb 3.0 to 3.6 22.4 (tcyc= 0.70 s) 640 (tcyc= 20 s) ad conversion time=32 tcyc (adcr2=0) (note 6-2) normal mode 2.4 to 3.6 128 (tcyc= 4.00 s) 640 (tcyc= 20 s) ad conversion time=32 tcyc (adcr2=0) (note6-2) power save mode 2.4 to 3.6 128 (tcyc= 4.00 s) 640 (tcyc= 20 s) 3.0 to 3.6 44.8 (tcyc= 0.70 s) 1280 (tcyc= 20 s) ad conversion time=64 tcyc (when adcr2=1) (note 6-2) normal mode 2.4 to 3.6 256 (tcyc= 4.00 s) 1280 (tcyc= 20 s) conversion time tcad ad conversion time=32 tcyc (adcr2=0) (note6-2) power save mode 2.4 to 3.6 256 (tcyc= 4.00 s) 1280 (tcyc= 20 s) s analog input voltage range vain 2.4 to 3.6 v ss v dd v iainh vain=v dd 2.4 to 3.6 1 analog port input current iainl an0(p00) to an4(p04), an5(p70) to an8(p73) vain=v ss 2.4 to 3.6 -1 a note 6-1: the quantization error ( 1/2lsb) is excluded from th e absolute accuracy value. note 6-2: the conversion time refers to the interval from th e time the instruction for starting the converter is issued till the time the complete digital value corresponding to the analog input value is loaded in the required register.
lc877816a/12a/08a no.a0635-16/21 consumption current characteristics at ta = -30c to +70c, v ss 1 = v ss 2 = 0v specification parameter symbol pins/ remarks conditions v dd [v] min typ max unit iddop(1) ? fmcf=4mhz cera mic resonator oscillation ? fsx?tal=32.768khz crystal oscillation ? system clock: cf 4mhz oscillation ? internal rc oscillation stopped. ? divider: 1/1 ? normal mode 2.4 to 3.6 1100 3200 iddop(2) ? fmcf=0hz (no oscillation) ? fsx?tal=32.768khz crystal oscillation ? system clock: rc oscillation ? divider: 1/1 ? normal mode 2.4 to 3.6 150 600 iddop(3) ? fmcf=0hz (no oscillation) ? fsx?tal=32.768khz crystal oscillation ? system clock: rc oscillation ? divider: 1/1 ? power save mode 2.4 to 3.6 50 225 iddop(4) ? fmcf=0hz (no oscillation) ? fsx?tal=32.768khz crystal oscillation ? system clock: rc oscillation ? divider: 1/2 ? power save mode 2.4 to 3.6 40 180 iddop(5) ? fmcf=0hz (no oscillation) ? fsx?tal=32.768khz crystal oscillation ? system clock: 32.768khz ? internal rc oscillation stopped. ? divider: 1/1 ? normal mode 2.4 to 3.6 15 60 iddop(6) ? fmcf=0hz (no oscillation) ? fsx?tal=32.768khz crystal oscillation ? system clock: 32.768khz ? internal rc oscillation stopped. ? divider: 1/1 ? power save mode 2.4 to 3.6 2.5 17 current consumption during normal operation (note 7-1) iddop(7) ? fmcf=0hz (no oscillation) ? fsx?tal=32.768khz crystal oscillation ? system clock: 32.768khz ? internal rc oscillation stopped. ? divider: 1/2 ? power save mode 2.4 to 3.6 1.5 15 iddhalt(1) halt mode ? fmcf=4mhz ceramic resonator oscillation ? fsx?tal=32.768khz crystal oscillation ? system clock: cf 4mhz oscillation ? internal rc oscillation stopped. ? divider: 1/1 ? normal mode 2.4 to 3.6 460 1600 iddhalt(2) halt mode ? fmcf=0h (oscillation stop) ? fsx?tal=32.768khz crystal oscillation ? system clock: rc oscillation ? divider: 1/1 ? normal mode 2.4 to 3.6 50 300 current consumption during halt mode (note 7-1) iddhalt(3) v dd 1= v dd 2= v2 halt mode ? fmcf=0h (oscillation stop) ? fsx?tal=32.768khz crystal oscillation ? system clock: rc oscillation ? divider: 1/1 ? power save mode 2.4 to 3.6 35 150 a note 7-1: the currents through the output transi stors and the pull-up mos transistors are ignored. continued on next page.
lc877816a/12a/08a no.a0635-17/21 continued from preceding page. specification parameter symbol pins/ remarks conditions v dd [v] min typ max unit iddhalt(4) halt mode ? fmcf=0h (oscillation stop) ? fsx?tal=32.768khz crystal oscillation ? system clock: rc oscillation ? divider: 1/2 ? power save mode 2.4 to 3.6 30 135 iddhalt(5) halt mode ? fmcf=0hz (oscillation stop) ? fsx?tal=32.768khz crystal oscillation ? system clock: 32.768khz ? internal rc oscillation stopped. ? divider: 1/1 ? normal mode 2.4 to 3.6 7.0 60 iddhalt(6) halt mode ? fmcf=0hz (oscillation stop) ? fsx?tal=32.768khz crystal oscillation ? system clock: 32.768khz ? internal rc oscillation stopped. ? divider: 1/1 ? power save mode 2.4 to 3.6 1.0 15 current consumption during halt mode (note 7-1) iddhalt(7) halt mode ? fmcf=0hz (oscillation stop) ? fsx?tal=32.768khz crystal oscillation ? system clock: 32.768khz ? internal rc oscillation stopped. ? divider: 1/2 ? power save mode 2.4 to 3.6 0.8 14 hold mode consumption current iddhold(1) hold mode ? cf1=v dd or open (when using external clock) 2.4 to 3.6 0.03 30 iddhold(2) date/time clock hold mode ? cf1=v dd or open (when using external clock) ? fmx?tal=32.768khz crystal oscillation ? internal rc oscillation stopped. ? divider: 1/1 ? normal mode 2.4 to 3.6 5.0 45 timer hold mode consumption current (note 7-1) iddhold(3) v dd 1= v dd 2= v2 date/time clock hold mode ? cf1=v dd or open (when using external clock) ? fmx?tal=32.768khz crystal oscillation ? internal rc oscillation stopped. ? divider: 1/1 ? power save mode 2.4 to 3.6 0.5 15 a note 7-1: the currents through the output transi stors and the pull-up mos transistors are ignored.
lc877816a/12a/08a no.a0635-18/21 main system clock oscillation circuit characteristics the characteristics in the table bellow is based on the following conditions: use the standard evaluation board sanyo has provided. use the peripheral parts with indicated value externally. the peripheral parts value is a recommended value of oscillator manufacturer table 1. main system clock oscillation circuit characteristics using ceramic resonator circuit parameters oscillation stabilizing time frequency manufacturer type oscillator c1 [pf] c2 [pf] rd [ ] operating supply voltage range[v] typ [ms] max [ms] notes smd cstcr4m00g53-r0 (15) ( 15) 1k 2.4 to 3.6 0.2 0.6 4.00mhz murata lead cstls4m00g53-b0 (15) (15) 2.2k 2.4 to 3.6 0.2 0.6 internal c1, c2 the oscillation stabilizing time is a period until the oscillation becomes stable after v dd becomes higher than minimum operating voltage. (see fig. 4) subsystem clock oscillation circuit characteristics the characteristics in the table bellow is based on the following conditions: use the standard evaluation board sanyo has provided. use the peripheral parts with indicated value externally. the peripheral parts value is a recommended value of oscillator manufacturer table 2. subsystem clock oscillation circu it characteristics using crystal oscillator circuit parameters oscillation stabilizing time frequency manufacturer oscillator c3 [pf] c4 [pf] rf [ ] rd2 [ ] operating supply voltage range [v] typ [s] max [s] notes 32.768khz epson toyocom mc-146 10 10 open 0 2.4 to 3.6 1 3 applicable cl value = 12.5pf the oscillation stabilizing time is a period until the oscillation becomes stable after executing the instruction which starts the sub-clock oscillation or after releasing the hold mode. (see fig. 4) notes: since the circuit pattern affects the oscillation frequ ency, place the oscillation-relate d parts as close to the oscillation pins as possible with the shortest possible pattern length. figure 1 ceramic oscillation circuit figure 2 crystal oscillation circuit figure 3 ac timing measurement point c1 c2 cf cf2 cf1 rd c3 rd2 c4 xt2 xt1 rf x?tal 0.5v dd
lc877816a/12a/08a no.a0635-19/21 reset time and oscillation stabilization time hold release signal and oscillation stabilization time figure 4 oscillation stabilizing time internal rc resonator oscillation cf1, cf2 xt1, xt2 operation mode hold release signal without hold release signal hold release signal valid tmscf tmsx?tal hold halt power supply res internal rc resonator oscillation cf1, cf2 xt1, xt2 operation mode reset time tmscf tmsx ? tal unfixed reset instruction execution v dd v dd limit 0v
lc877816a/12a/08a no.a0635-20/21 figure 5 reset circuit figure 6 serial i/o waveforms n ote: select c res and r res value to assure that at least 200 s reset time is generated after the v dd becomes higher than the minimum operating voltage. c res v dd r res res sioclk: datain: dataout: di0 di1 di2 di3 di4 di5 di6 di7 di8 do0 do1 do2 do3 do4 do5 do6 do7 do8 data ram transfer period (only sio0) sioclk: datain: dataout: tsck tsckl tsckh tsdi thdi tddo sioclk: datain: dataout: tddo tsdi thdi tsckl tsckha data ram transfer period (only sio0)
lc877816a/12a/08a no.a0635-21/21 figure 7 pulse input timing signal waveform ps tpil tpih this catalog provides information as of august, 2007. specifications and information herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsibil ity for equipment failures that result from using products at values that exceed, even momentarily, rated v alues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qua lity high-reliability products, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these probabilistic failures or malfunction could give rise to accident s or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the us e of the technical information and products mentioned above. information (including circuit diagrams and circuit par ameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained he rein are subject to change without notice due to product/technology improvement, etc. when designing equip ment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control l aws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd.

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